1. Field
The present invention relates generally to near field communication (NFC). More specifically, the present invention relates to clock and data recovery for NFC transceivers.
2. Background
Near Field Communication (NFC) is wireless technology that can enable for short range exchange of information between two or more devices. Devices capable of NFC can simplify presence-oriented transactions to enable for rapid and more secure exchange of information, for example, as in purchases for goods and services, or the exchange of information therein.
As a person skilled in the art will appreciate and understand, NFC technologies communicate over magnetic field induction, where at least two loop antennas are located within each other's “near field,” effectively forming an air-core transformer that operates within a globally available and unlicensed radio frequency which, as indicated, is an industrial, scientific and medical (ISM) band of 13.56 MHz, with a band width of almost two (2) MHz.
Conventional NFC transceivers utilize two separate phase lock loops (PLLs) for frequency synthesis and clock and data recovery (CDR). More specifically, conventional devices may utilize a high-frequency PLL to enable for oversampling of a transmitter output in an initiator mode, and a low-power PLL to recover a clock from an input signal in a tag mode. As will be appreciated by a person having ordinary skill in the art, utilization of two separate PLLs consumes a large area and increases the bill of materials (BOM) due to the increased number of external PLL loop filter components. A need exists for methods, systems, and devices for an NFC transceiver configured to utilize a single phased-locked loop, which may operate in both an initiator mode and a tag mode. Further, a need exists for the phase-locked loop to operate and detect signals associated with NFC and RFID standards including a 100% amplitude-shift keying signal.